diff options
| author | Richard Henderson <rth@twiddle.net> | 2011-10-18 09:24:43 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2011-10-26 14:00:19 -0700 |
| commit | 793a137a41ad4125011c7022cf16a1baa40a5ab6 (patch) | |
| tree | 10b81a781533fb487d02e67b3cd9aae23f6c1a39 /target-sparc/translate.c | |
| parent | add545ab11450c7049468fccdcd362b47740d9fe (diff) | |
target-sparc: Implement BMASK/BSHUFFLE.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-sparc/translate.c')
| -rw-r--r-- | target-sparc/translate.c | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 685a9070fe..50fc587865 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -4192,8 +4192,13 @@ static void disas_sparc_insn(DisasContext * dc) gen_movl_TN_reg(rd, cpu_dst); break; case 0x019: /* VIS II bmask */ - // XXX - goto illegal_insn; + CHECK_FPU_FEATURE(dc, VIS2); + cpu_src1 = get_src1(insn, cpu_src1); + cpu_src2 = get_src1(insn, cpu_src2); + tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); + tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, cpu_dst, 32, 32); + gen_movl_TN_reg(rd, cpu_dst); + break; case 0x020: /* VIS I fcmple16 */ CHECK_FPU_FEATURE(dc, VIS1); cpu_src1_64 = gen_load_fpr_D(dc, rs1); @@ -4314,8 +4319,9 @@ static void disas_sparc_insn(DisasContext * dc) gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpmerge); break; case 0x04c: /* VIS II bshuffle */ - // XXX - goto illegal_insn; + CHECK_FPU_FEATURE(dc, VIS2); + gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_bshuffle); + break; case 0x04d: /* VIS I fexpand */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fexpand); |