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authorblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2008-03-18 18:08:25 +0000
committerblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2008-03-18 18:08:25 +0000
commitd35527d9f9ca7b0c99de06eb720cb35ee56ac5f6 (patch)
treecd85b4f8ba93fff68c95339bb405eac115d82411 /target-sparc/op_helper.c
parent1f5063fb9756805efcd8c5a438ab747f36f796d9 (diff)
Convert CCR and CWP ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4086 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc/op_helper.c')
-rw-r--r--target-sparc/op_helper.c21
1 files changed, 21 insertions, 0 deletions
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index 18a01f5d75..b47e50e52e 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -1636,6 +1636,27 @@ target_ulong helper_rdpsr(void)
}
#else
+target_ulong helper_rdccr(void)
+{
+ return GET_CCR(env);
+}
+
+void helper_wrccr(target_ulong new_ccr)
+{
+ PUT_CCR(env, new_ccr);
+}
+
+// CWP handling is reversed in V9, but we still use the V8 register
+// order.
+target_ulong helper_rdcwp(void)
+{
+ return GET_CWP64(env);
+}
+
+void helper_wrcwp(target_ulong new_cwp)
+{
+ PUT_CWP64(env, new_cwp);
+}
// This function uses non-native bit order
#define GET_FIELD(X, FROM, TO) \