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authorbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2006-06-21 18:37:05 +0000
committerbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2006-06-21 18:37:05 +0000
commit65ce8c2fb438c8685dbcd28784a0b0ba2b484e5f (patch)
treee5c5f2f4c38d8d2d22101bb9070488c32885cc12 /target-sparc/cpu.h
parentee6c0b51e97c8bcad32181f42e63765b18c30354 (diff)
soft floats for SPARC (Blue Swirl)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2000 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc/cpu.h')
-rw-r--r--target-sparc/cpu.h10
1 files changed, 4 insertions, 6 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 28efab758f..c6d5621b11 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -12,7 +12,7 @@
#define TARGET_FPREGS 64
#define TARGET_PAGE_BITS 12 /* XXX */
#endif
-#define TARGET_FPREG_T float
+#define TARGET_FPREG_T float32
#include "cpu-defs.h"
@@ -146,7 +146,7 @@
typedef struct CPUSPARCState {
target_ulong gregs[8]; /* general registers */
target_ulong *regwptr; /* pointer to current register window */
- TARGET_FPREG_T fpr[TARGET_FPREGS]; /* floating point registers */
+ float32 fpr[TARGET_FPREGS]; /* floating point registers */
target_ulong pc; /* program counter */
target_ulong npc; /* next program counter */
target_ulong y; /* multiply/divide register */
@@ -187,8 +187,8 @@ typedef struct CPUSPARCState {
uint32_t mmuregs[16];
#endif
/* temporary float registers */
- float ft0, ft1;
- double dt0, dt1;
+ float32 ft0, ft1;
+ float64 dt0, dt1;
float_status fp_status;
#if defined(TARGET_SPARC64)
#define MAXTL 4
@@ -236,8 +236,6 @@ typedef struct CPUSPARCState {
CPUSPARCState *cpu_sparc_init(void);
int cpu_sparc_exec(CPUSPARCState *s);
int cpu_sparc_close(CPUSPARCState *s);
-void cpu_get_fp64(uint64_t *pmant, uint16_t *pexp, double f);
-double cpu_put_fp64(uint64_t mant, uint16_t exp);
/* Fake impl 0, version 4 */
#define GET_PSR(env) ((0 << 28) | (4 << 24) | (env->psr & PSR_ICC) | \