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authorblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2007-11-07 17:03:37 +0000
committerblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2007-11-07 17:03:37 +0000
commit6d5f237a592706773733e71e6da81dcd625fbb24 (patch)
treefd4799df1f00634075545a379697f9daac8c9166 /target-sparc/cpu.h
parentbc4edd79ee56bfa1c023006cf5a95631e0a52f18 (diff)
CPU specific boot mode (Robert Reif)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3542 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc/cpu.h')
-rw-r--r--target-sparc/cpu.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 51cbd4c328..0e5a4e2227 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -147,7 +147,6 @@
/* MMU */
#define MMU_E (1<<0)
#define MMU_NF (1<<1)
-#define MMU_BM (1<<14)
#define PTE_ENTRYTYPE_MASK 3
#define PTE_ACCESS_MASK 0x1c
@@ -200,6 +199,7 @@ typedef struct CPUSPARCState {
int interrupt_index;
int interrupt_request;
int halted;
+ uint32_t mmu_bm;
/* NOTE: we allow 8 more registers to handle wrapping */
target_ulong regbase[NWINDOWS * 16 + 8];