diff options
| author | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-08-04 10:50:30 +0000 |
|---|---|---|
| committer | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-08-04 10:50:30 +0000 |
| commit | 327ac2e797ed57d7231d44c77a7473d62efe0989 (patch) | |
| tree | 1809a94735d69b1ed2aa5fa39ddfdd76b0921df5 /target-sparc/cpu.h | |
| parent | ccf1d14a1e37abe1f0da162c00a8941963b47a4c (diff) | |
Fix Sparc32 interrupt handling
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3110 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sparc/cpu.h')
| -rw-r--r-- | target-sparc/cpu.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 600b37ba5e..e469f041a1 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -181,7 +181,8 @@ typedef struct CPUSPARCState { int psrs; /* supervisor mode (extracted from PSR) */ int psrps; /* previous supervisor mode */ int psret; /* enable traps */ - uint32_t psrpil; /* interrupt level */ + uint32_t psrpil; /* interrupt blocking level */ + uint32_t pil_in; /* incoming interrupt level bitmap */ int psref; /* enable fpu */ target_ulong version; jmp_buf jmp_env; @@ -306,6 +307,7 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, void do_tick_set_count(void *opaque, uint64_t count); uint64_t do_tick_get_count(void *opaque); void do_tick_set_limit(void *opaque, uint64_t limit); +void cpu_check_irqs(CPUSPARCState *env); #define CPUState CPUSPARCState #define cpu_init cpu_sparc_init |