diff options
| author | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2006-06-14 15:02:05 +0000 |
|---|---|---|
| committer | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2006-06-14 15:02:05 +0000 |
| commit | eda9b09b1df1efea4275baadb9743ff5124bd7c2 (patch) | |
| tree | 8f7e9abf255787610f90f4a0be68c3c42dc6c50c /target-sh4/cpu.h | |
| parent | 191f9a93f48ba8859bbbc8d5ac9b401568c2c6f4 (diff) | |
sh4 fmov et al instructions (amatus)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1971 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sh4/cpu.h')
| -rw-r--r-- | target-sh4/cpu.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index d99ff8e802..c71af74373 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -27,6 +27,8 @@ #include "cpu-defs.h" +#include "softfloat.h" + #define TARGET_PAGE_BITS 12 /* 4k XXXXX */ #define SR_MD (1 << 30) @@ -90,6 +92,10 @@ typedef struct CPUSH4State { uint32_t fpscr; /* floating point status/control register */ uint32_t fpul; /* floating point communication register */ + /* temporary float registers */ + float32 ft0, ft1; + float64 dt0, dt1; + /* Those belong to the specific unit (SH7750) but are handled here */ uint32_t mmucr; /* MMU control register */ uint32_t pteh; /* page table entry high register */ |