diff options
author | Richard Henderson <rth@twiddle.net> | 2012-08-31 10:53:49 -0700 |
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committer | Richard Henderson <rth@twiddle.net> | 2013-01-05 12:18:44 -0800 |
commit | 5550359f07b54d6fb6f38ee5dcbc198cff42bf51 (patch) | |
tree | 25b2c78dcf741e2b8be948d7612e48200a926dd1 /target-s390x/translate.c | |
parent | 7a6c7067f034c5b887cda5e45ef660fe50ebbd1b (diff) |
target-s390: Implement COMPARE AND BRANCH
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-s390x/translate.c')
-rw-r--r-- | target-s390x/translate.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/target-s390x/translate.c b/target-s390x/translate.c index c87d97ffe2..d6f7121a2e 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -1427,6 +1427,34 @@ static ExitStatus op_bx64(DisasContext *s, DisasOps *o) return help_branch(s, &c, is_imm, imm, o->in2); } +static ExitStatus op_cj(DisasContext *s, DisasOps *o) +{ + int imm, m3 = get_field(s->fields, m3); + bool is_imm; + DisasCompare c; + + /* Bit 3 of the m3 field is reserved and should be zero. + Choose to ignore it wrt the ltgt_cond table above. */ + c.cond = ltgt_cond[m3 & 14]; + if (s->insn->data) { + c.cond = tcg_unsigned_cond(c.cond); + } + c.is_64 = c.g1 = c.g2 = true; + c.u.s64.a = o->in1; + c.u.s64.b = o->in2; + + is_imm = have_field(s->fields, i4); + if (is_imm) { + imm = get_field(s->fields, i4); + } else { + imm = 0; + o->out = get_address(s, 0, get_field(s->fields, b4), + get_field(s->fields, d4)); + } + + return help_branch(s, &c, is_imm, imm, o->out); +} + static ExitStatus op_ceb(DisasContext *s, DisasOps *o) { gen_helper_ceb(cc_op, cpu_env, o->in1, o->in2); |