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authorPeter Maydell <peter.maydell@linaro.org>2015-10-21 15:07:42 +0100
committerPeter Maydell <peter.maydell@linaro.org>2015-10-21 15:07:42 +0100
commit8bfaa25fce2c22060a17501980943538801056de (patch)
treebc98ce8c11d3d30cad8b2937bb1ec61cf64fb2a8 /target-s390x/cpu.h
parent426c0df9e3e6e64c7ea489092c57088ca4d227d0 (diff)
parent1cd4e0f6f0a6b1978a5868b41d4faae2071dc4ee (diff)
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20151021-v2' into staging
More s390x patches. The first ones are fixes: A regression, missed compat and a missed part of the SIMD support. The others contain optimizations and cleanup. # gpg: Signature made Wed 21 Oct 2015 11:24:48 BST using RSA key ID C6F02FAF # gpg: Good signature from "Cornelia Huck <huckc@linux.vnet.ibm.com>" # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" * remotes/cohuck/tags/s390x-20151021-v2: s390x/cmma: clean up cmma reset s390x: reset crypto only on clear reset and QEMU reset s390x: machine reset function with new ipl cpu handling s390x/ipl: we always have an ipl device s390x: unify device reset during subsystem_reset() s390x: flagify mcic values s390x/kvm: Fix vector validity bit in device machine checks s390x/virtio-ccw: fix 2.4 virtio compat util/qemu-config: fix missing machine command line options Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-s390x/cpu.h')
-rw-r--r--target-s390x/cpu.h65
1 files changed, 60 insertions, 5 deletions
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index e4de8632f3..658cd9d554 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -1160,12 +1160,13 @@ int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
int vq, bool assign);
int kvm_s390_cpu_restart(S390CPU *cpu);
int kvm_s390_get_memslot_count(KVMState *s);
-void kvm_s390_clear_cmma_callback(void *opaque);
+void kvm_s390_cmma_reset(void);
int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state);
void kvm_s390_reset_vcpu(S390CPU *cpu);
int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit, uint64_t *hw_limit);
void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu);
int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu);
+void kvm_s390_crypto_reset(void);
#else
static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
uint16_t subchannel_nr,
@@ -1189,7 +1190,7 @@ static inline int kvm_s390_cpu_restart(S390CPU *cpu)
{
return -ENOSYS;
}
-static inline void kvm_s390_clear_cmma_callback(void *opaque)
+static inline void kvm_s390_cmma_reset(void)
{
}
static inline int kvm_s390_get_memslot_count(KVMState *s)
@@ -1215,6 +1216,9 @@ static inline int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu)
{
return 0;
}
+static inline void kvm_s390_crypto_reset(void)
+{
+}
#endif
static inline int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit)
@@ -1225,11 +1229,10 @@ static inline int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit)
return 0;
}
-static inline void cmma_reset(S390CPU *cpu)
+static inline void s390_cmma_reset(void)
{
if (kvm_enabled()) {
- CPUState *cs = CPU(cpu);
- kvm_s390_clear_cmma_callback(cs->kvm_state);
+ kvm_s390_cmma_reset();
}
}
@@ -1261,6 +1264,13 @@ static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
}
+static inline void s390_crypto_reset(void)
+{
+ if (kvm_enabled()) {
+ kvm_s390_crypto_reset();
+ }
+}
+
#ifdef CONFIG_KVM
static inline bool vregs_needed(void *opaque)
{
@@ -1275,4 +1285,49 @@ static inline bool vregs_needed(void *opaque)
return 0;
}
#endif
+
+/* machine check interruption code */
+
+/* subclasses */
+#define MCIC_SC_SD 0x8000000000000000ULL
+#define MCIC_SC_PD 0x4000000000000000ULL
+#define MCIC_SC_SR 0x2000000000000000ULL
+#define MCIC_SC_CD 0x0800000000000000ULL
+#define MCIC_SC_ED 0x0400000000000000ULL
+#define MCIC_SC_DG 0x0100000000000000ULL
+#define MCIC_SC_W 0x0080000000000000ULL
+#define MCIC_SC_CP 0x0040000000000000ULL
+#define MCIC_SC_SP 0x0020000000000000ULL
+#define MCIC_SC_CK 0x0010000000000000ULL
+
+/* subclass modifiers */
+#define MCIC_SCM_B 0x0002000000000000ULL
+#define MCIC_SCM_DA 0x0000000020000000ULL
+#define MCIC_SCM_AP 0x0000000000080000ULL
+
+/* storage errors */
+#define MCIC_SE_SE 0x0000800000000000ULL
+#define MCIC_SE_SC 0x0000400000000000ULL
+#define MCIC_SE_KE 0x0000200000000000ULL
+#define MCIC_SE_DS 0x0000100000000000ULL
+#define MCIC_SE_IE 0x0000000080000000ULL
+
+/* validity bits */
+#define MCIC_VB_WP 0x0000080000000000ULL
+#define MCIC_VB_MS 0x0000040000000000ULL
+#define MCIC_VB_PM 0x0000020000000000ULL
+#define MCIC_VB_IA 0x0000010000000000ULL
+#define MCIC_VB_FA 0x0000008000000000ULL
+#define MCIC_VB_VR 0x0000004000000000ULL
+#define MCIC_VB_EC 0x0000002000000000ULL
+#define MCIC_VB_FP 0x0000001000000000ULL
+#define MCIC_VB_GR 0x0000000800000000ULL
+#define MCIC_VB_CR 0x0000000400000000ULL
+#define MCIC_VB_ST 0x0000000100000000ULL
+#define MCIC_VB_AR 0x0000000040000000ULL
+#define MCIC_VB_PR 0x0000000000200000ULL
+#define MCIC_VB_FC 0x0000000000100000ULL
+#define MCIC_VB_CT 0x0000000000020000ULL
+#define MCIC_VB_CC 0x0000000000010000ULL
+
#endif