diff options
| author | Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com> | 2016-09-29 00:11:52 +0530 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2016-10-05 11:05:28 +1100 |
| commit | 6358320228010e0425955ca6ed32ac878b24f12a (patch) | |
| tree | 0bad7870073c0984934d6d6c47e2c893f456a7c3 /target-ppc | |
| parent | bac3bf287ab60e264b636f5f00c116a19b655762 (diff) | |
target-ppc: Implement mfvsrld instruction
mfvsrld: Move From VSR Lower Doubleword
Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/translate/vsx-impl.inc.c | 17 | ||||
| -rw-r--r-- | target-ppc/translate/vsx-ops.inc.c | 1 |
2 files changed, 18 insertions, 0 deletions
diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c index eee6052d03..b669e8c818 100644 --- a/target-ppc/translate/vsx-impl.inc.c +++ b/target-ppc/translate/vsx-impl.inc.c @@ -217,6 +217,23 @@ static void gen_##name(DisasContext *ctx) \ MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode))) MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)]) +static void gen_mfvsrld(DisasContext *ctx) +{ + if (xS(ctx->opcode) < 32) { + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + } else { + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + } + + tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], cpu_vsrl(xS(ctx->opcode))); +} + #endif static void gen_xxpermdi(DisasContext *ctx) diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c index 414b73bd10..3b296f8efd 100644 --- a/target-ppc/translate/vsx-ops.inc.c +++ b/target-ppc/translate/vsx-ops.inc.c @@ -22,6 +22,7 @@ GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207), #if defined(TARGET_PPC64) GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207), GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207), +GEN_HANDLER_E(mfvsrld, 0X1F, 0x13, 0x09, 0x0000F800, PPC_NONE, PPC2_ISA300), #endif #define GEN_XX1FORM(name, opc2, opc3, fl2) \ |