diff options
| author | Nathan Froyd <froydnj@codesourcery.com> | 2010-02-23 11:55:14 -0800 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2010-02-27 16:10:49 +0100 |
| commit | e6bba2ef49670167694b227df13fc8461debbcd5 (patch) | |
| tree | 37d30bc9f4320bcf0ad0ae2fe1d6a7a1e0272019 /target-ppc | |
| parent | e3b283e94acc6fc304cc54971ee74c5a445a96b6 (diff) | |
target-ppc: fix SPE evcmp* instructions
The CRF_{CH,CL,CH_OR_CL,CH_AND_CL} constants were all off by one bit
position. Because of this, the SPE evcmp* family of instructions would
store values in the result condition register that were also off by one
bit position.
Fixed by using the CRF_{LT,GT,EQ,SO} constants for the shift amounts.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/cpu.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index d15bba18d4..63aeb86070 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -834,10 +834,10 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) #define CRF_GT 2 #define CRF_EQ 1 #define CRF_SO 0 -#define CRF_CH (1 << 4) -#define CRF_CL (1 << 3) -#define CRF_CH_OR_CL (1 << 2) -#define CRF_CH_AND_CL (1 << 1) +#define CRF_CH (1 << CRF_LT) +#define CRF_CL (1 << CRF_GT) +#define CRF_CH_OR_CL (1 << CRF_EQ) +#define CRF_CH_AND_CL (1 << CRF_SO) /* XER definitions */ #define XER_SO 31 |