diff options
| author | Aurelien Jarno <aurelien@aurel32.net> | 2011-05-23 22:35:37 +0200 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2011-05-23 22:35:37 +0200 |
| commit | 5db070eb1ab902572e46ed09e5947ffe504522bc (patch) | |
| tree | 6bfd837872aad6fb3f07a283208befa1dbba1c39 /target-ppc | |
| parent | 05c8a1e423736006580e4dd2bd94d0faafc9afdc (diff) | |
| parent | decb471488dd9e7e7ab9957f120cb501c4489f63 (diff) | |
Merge branch 'ppc-next' of git://repo.or.cz/qemu/agraf
* 'ppc-next' of git://repo.or.cz/qemu/agraf:
Fix a bug in mtsr/mtsrin emulation on ppc64
pSeries: Clean up write-only variables
w32: Fix compilation and replace non-portable usage of ulong
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/cpu.h | 4 | ||||
| -rw-r--r-- | target-ppc/helper.c | 9 |
2 files changed, 6 insertions, 7 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 7a6a7dfa57..8e4582f6ab 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1929,8 +1929,8 @@ static inline void cpu_set_tls(CPUState *env, target_ulong newtls) #if !defined(CONFIG_USER_ONLY) static inline int booke206_tlbe_id(CPUState *env, ppcemb_tlb_t *tlbe) { - ulong tlbel = (ulong)tlbe; - ulong tlbl = (ulong)env->tlb; + uintptr_t tlbel = (uintptr_t)tlbe; + uintptr_t tlbl = (uintptr_t)env->tlb; return (tlbel - tlbl) / sizeof(env->tlb[0]); } diff --git a/target-ppc/helper.c b/target-ppc/helper.c index 4238be6133..4700632931 100644 --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -606,7 +606,7 @@ static inline int _find_pte(CPUState *env, mmu_ctx_t *ctx, int is_64b, int h, r = pte64_check(ctx, pte0, pte1, h, rw, type); LOG_MMU("Load pte from " TARGET_FMT_lx " => " TARGET_FMT_lx " " TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n", - pteg_base + (i * 16), pte0, pte1, (int)(pte0 & 1), h, + pteg_off + (i * 16), pte0, pte1, (int)(pte0 & 1), h, (int)((pte0 >> 1) & 1), ctx->ptem); } else #endif @@ -621,7 +621,7 @@ static inline int _find_pte(CPUState *env, mmu_ctx_t *ctx, int is_64b, int h, r = pte32_check(ctx, pte0, pte1, h, rw, type); LOG_MMU("Load pte from " TARGET_FMT_lx " => " TARGET_FMT_lx " " TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n", - pteg_base + (i * 8), pte0, pte1, (int)(pte0 >> 31), h, + pteg_off + (i * 8), pte0, pte1, (int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1), ctx->ptem); } switch (r) { @@ -918,8 +918,7 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx, if (eaddr != 0xEFFFFFFF) LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx - " hash=" TARGET_FMT_plx " pg_addr=" - TARGET_FMT_plx "\n", env->htab_base, + " hash=" TARGET_FMT_plx "\n", env->htab_base, env->htab_mask, vsid, ctx->ptem, ctx->hash[1]); ret2 = find_pte(env, ctx, 1, rw, type, target_page_bits); @@ -2140,7 +2139,7 @@ void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value) /* VSID = VSID */ rs |= (value & 0xfffffff) << 12; /* flags = flags */ - rs |= ((value >> 27) & 0xf) << 9; + rs |= ((value >> 27) & 0xf) << 8; ppc_store_slb(env, rb, rs); } else |