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authoraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2009-03-07 20:57:47 +0000
committeraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2009-03-07 20:57:47 +0000
commit0497d2f4e49f38539a987e429a0a6b003ec79168 (patch)
tree079ecdea78c1ff888bebb2418c9dd2ec529d4df3 /target-ppc
parent8eee0af947cafdce5668abb6b7545f3887624ba8 (diff)
Fix mfcr on ppc64-softmmu
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6758 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc')
-rw-r--r--target-ppc/translate.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 386343ede9..e400cf2da1 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -3855,8 +3855,8 @@ GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
if (likely(crm && ((crm & (crm - 1)) == 0))) {
crn = ctz32 (crm);
tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
- tcg_gen_shli_i32(cpu_gpr[rD(ctx->opcode)],
- cpu_gpr[rD(ctx->opcode)], crn * 4);
+ tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
+ cpu_gpr[rD(ctx->opcode)], crn * 4);
}
} else {
gen_helper_load_cr(cpu_gpr[rD(ctx->opcode)]);