diff options
| author | Hervé Poussineau <hpoussin@reactos.org> | 2011-06-14 23:27:56 +0200 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2011-06-17 02:58:24 +0200 |
| commit | 826e7b827c5f83e88d5aa84c0bf0b3459f28ec35 (patch) | |
| tree | 11bf567b813574a8dcc04334cde1a2189129dfc0 /target-ppc | |
| parent | b0fb84236da4a36a852010b6b5d5d3ca497a2b68 (diff) | |
target-ppc: Handle memory-forced I/O controller access
On at least the PowerPC 601, a direct-store (T=1) with bus unit ID 0x07F
is special-cased as memory-forced I/O controller access. It is supposed
to be checked immediately if T=1, bypassing all protection mechanisms
and acting cache-inhibited and global.
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Simplified by avoiding reindentation. Added explanatory comments.
Cc: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/helper.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/target-ppc/helper.c b/target-ppc/helper.c index cf2a368b57..2944b062a5 100644 --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -949,8 +949,24 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx, ret = -3; } } else { + target_ulong sr; LOG_MMU("direct store...\n"); /* Direct-store segment : absolutely *BUGGY* for now */ + + /* Direct-store implies a 32-bit MMU. + * Check the Segment Register's bus unit ID (BUID). + */ + sr = env->sr[eaddr >> 28]; + if ((sr & 0x1FF00000) >> 20 == 0x07f) { + /* Memory-forced I/O controller interface access */ + /* If T=1 and BUID=x'07F', the 601 performs a memory access + * to SR[28-31] LA[4-31], bypassing all protection mechanisms. + */ + ctx->raddr = ((sr & 0xF) << 28) | (eaddr & 0x0FFFFFFF); + ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return 0; + } + switch (type) { case ACCESS_INT: /* Integer load/store : only access allowed */ |