diff options
author | Alexander Graf <agraf@suse.de> | 2014-01-19 17:26:33 +0100 |
---|---|---|
committer | Alexander Graf <agraf@suse.de> | 2014-06-16 13:24:34 +0200 |
commit | c80d1df5083846396ab5120731a76a9d62900fda (patch) | |
tree | 7597dad7896cbcd8e2581767bc49c3eec4e20841 /target-ppc | |
parent | 3016dca06cba0ef9511f1c81c7e73bfc805fb254 (diff) |
PPC: Fix TCG chunks that don't free their temps
We want to make sure that every instruction cleans up after itself and
clears every temporary it allocated.
While checking whether this is already the case, I came across a few
cases where it isn't. This patch fixes every translation I found that
doesn't free their allocated temporaries.
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc')
-rw-r--r-- | target-ppc/translate.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 0d5a9a57c9..1603995e06 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -1224,6 +1224,7 @@ static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, } tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ tcg_gen_add_tl(t0, t0, inv1); + tcg_temp_free(inv1); tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ tcg_temp_free(t1); tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ @@ -3920,6 +3921,9 @@ static inline void gen_bcond(DisasContext *ctx, int type) gen_update_nip(ctx, ctx->nip); tcg_gen_exit_tb(0); } + if (type == BCOND_LR || type == BCOND_CTR) { + tcg_temp_free(target); + } } static void gen_bc(DisasContext *ctx) @@ -4367,6 +4371,7 @@ static void gen_mtmsr(DisasContext *ctx) tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); #endif gen_helper_store_msr(cpu_env, msr); + tcg_temp_free(msr); /* Must stop the translation as machine state (may have) changed */ /* Note that mtmsr is not always defined as context-synchronizing */ gen_stop_exception(ctx); @@ -6501,6 +6506,7 @@ static void gen_tlbsx_booke206(DisasContext *ctx) tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); gen_helper_booke206_tlbsx(cpu_env, t0); + tcg_temp_free(t0); #endif } @@ -6534,6 +6540,7 @@ static void gen_tlbivax_booke206(DisasContext *ctx) gen_addr_reg_index(ctx, t0); gen_helper_booke206_tlbivax(cpu_env, t0); + tcg_temp_free(t0); #endif } |