diff options
| author | Tom Musta <tommusta@gmail.com> | 2013-11-01 08:21:14 -0500 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2013-12-20 01:57:55 +0100 |
| commit | 897e61d13777a5995d3cd12fcaf44eb4bbb5439c (patch) | |
| tree | dd8ba97e0bea322580e4137878ebc5ae7545e304 /target-ppc | |
| parent | ca03b46765d4633f5746764696058b0cb33ac487 (diff) | |
Add lxvw4x
This patch adds the Load VSX Vector Word*4 Indexed (lxvw4x)
instruction.
V2: changed to use deposit_i64 per Richard Henderson's review.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/translate.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 23d2e09aa2..62e74a65a4 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -7049,6 +7049,34 @@ static void gen_lxvdsx(DisasContext *ctx) tcg_temp_free(EA); } +static void gen_lxvw4x(DisasContext *ctx) +{ + TCGv EA, tmp; + TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode)); + TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode)); + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + gen_set_access_type(ctx, ACCESS_INT); + EA = tcg_temp_new(); + tmp = tcg_temp_new(); + gen_addr_reg_index(ctx, EA); + gen_qemu_ld32u(ctx, tmp, EA); + tcg_gen_addi_tl(EA, EA, 4); + gen_qemu_ld32u(ctx, xth, EA); + tcg_gen_deposit_i64(xth, xth, tmp, 32, 32); + + tcg_gen_addi_tl(EA, EA, 4); + gen_qemu_ld32u(ctx, tmp, EA); + tcg_gen_addi_tl(EA, EA, 4); + gen_qemu_ld32u(ctx, xtl, EA); + tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32); + + tcg_temp_free(EA); + tcg_temp_free(tmp); +} + static void gen_stxvd2x(DisasContext *ctx) { TCGv EA; @@ -9535,6 +9563,7 @@ GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23), GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX), GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX), GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX), +GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX), GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX), |