diff options
| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2016-06-21 23:48:52 +0200 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2016-06-23 12:43:54 +1000 |
| commit | b781537560e3b968b6fe1395e3d07bd67f0009ba (patch) | |
| tree | 6ebdcbaedc66c5c6964d461cfecf8cd83efb89e6 /target-ppc/translate_init.c | |
| parent | 9b2fadda3e0196ffd485adde4fe9cdd6fae35300 (diff) | |
ppc: Add real mode CI load/store instructions for P7 and P8
Those instructions are only available in hypervisor real mode and
allow cache inhibited garded access to devices in that mode.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[clg: fixed checkpatch.pl errors ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target-ppc/translate_init.c')
| -rw-r--r-- | target-ppc/translate_init.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 01a490ca89..15d8db79b4 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8404,7 +8404,8 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | PPC_SEGMENT_64B | PPC_SLBI | - PPC_POPCNTB | PPC_POPCNTWD; + PPC_POPCNTB | PPC_POPCNTWD | + PPC_CILDST; pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | @@ -8485,7 +8486,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | PPC_SEGMENT_64B | PPC_SLBI | - PPC_POPCNTB | PPC_POPCNTWD; + PPC_POPCNTB | PPC_POPCNTWD | + PPC_CILDST; pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | |