diff options
author | Thomas Monjalon <thomas@monjalon.net> | 2009-10-15 19:01:19 +0200 |
---|---|---|
committer | Aurelien Jarno <aurelien@aurel32.net> | 2009-10-18 16:15:34 +0200 |
commit | 8daf178168815e5af502a0fab343d23d7e1e4230 (patch) | |
tree | 0f29ec896050f8a6845fbbaf3f2da2ba5b707063 /target-ppc/translate_init.c | |
parent | dcc65026c4bd8b6fc569b3c1b990fbc8001f8f02 (diff) |
target-ppc: better support of e300 CPU core
Declare HID2 register.
Use high BATs for e300 (8 instead of 4).
Fix index of high BATs registers.
Before the fix, IBAT4-7 were overwriting IBAT0-3.
Signed-off-by: François Armand <francois.armand@os4i.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-ppc/translate_init.c')
-rw-r--r-- | target-ppc/translate_init.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 79d3b4ca9a..910b4d9987 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -233,7 +233,7 @@ static void spr_write_ibatu (void *opaque, int sprn, int gprn) static void spr_write_ibatu_h (void *opaque, int sprn, int gprn) { - TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT4U) / 2); + TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); gen_helper_store_ibatu(t0, cpu_gpr[gprn]); tcg_temp_free_i32(t0); } @@ -247,7 +247,7 @@ static void spr_write_ibatl (void *opaque, int sprn, int gprn) static void spr_write_ibatl_h (void *opaque, int sprn, int gprn) { - TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT4L) / 2); + TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); gen_helper_store_ibatl(t0, cpu_gpr[gprn]); tcg_temp_free_i32(t0); } @@ -4166,8 +4166,14 @@ static void init_proc_e300 (CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_HID2, "HID2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); /* Memory management */ gen_low_BATs(env); + gen_high_BATs(env); gen_6xx_7xx_soft_tlb(env, 64, 2); init_excp_603(env); env->dcache_line_size = 32; |