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authorAlexey Kardashevskiy <aik@ozlabs.ru>2014-06-04 22:50:43 +1000
committerAlexander Graf <agraf@suse.de>2014-06-16 13:24:43 +0200
commitc36c97f8804bbc2cd731f37a159ecdf618600871 (patch)
tree39ca3ece62d803f2e8da9861d1b82efdc4d7de36 /target-ppc/translate_init.c
parent077850b037eea63d9b01db96dd0cb65a46dd0f0f (diff)
target-ppc: Add PMC7/8 to 970 class
Compared to PowerISA-compliant CPUs, 970 family has most of them plus PMC7/8 which are only present on 970 but not on POWER5 and later CPUs. Since we are changing SPRs for Book3s/970 families, let's add them too. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/translate_init.c')
-rw-r--r--target-ppc/translate_init.c26
1 files changed, 26 insertions, 0 deletions
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index bffed905a7..568bf9cf8f 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7449,6 +7449,30 @@ static void gen_spr_book3s_pmu_user(CPUPPCState *env)
0x00000000);
}
+static void gen_spr_970_pmu_sup(CPUPPCState *env)
+{
+ spr_register(env, SPR_970_PMC7, "PMC7",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_970_PMC8, "PMC8",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+static void gen_spr_970_pmu_user(CPUPPCState *env)
+{
+ spr_register(env, SPR_970_UPMC7, "UPMC7",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, &spr_write_ureg,
+ 0x00000000);
+ spr_register(env, SPR_970_UPMC8, "UPMC8",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, &spr_write_ureg,
+ 0x00000000);
+}
+
static void gen_spr_power5p_ear(CPUPPCState *env)
{
/* External access control */
@@ -7471,6 +7495,8 @@ static void init_proc_970 (CPUPPCState *env)
gen_spr_970_hior(env);
gen_low_BATs(env);
gen_spr_book3s_common(env);
+ gen_spr_970_pmu_sup(env);
+ gen_spr_970_pmu_user(env);
gen_spr_power5p_ear(env);