diff options
| author | Alexey Kardashevskiy <aik@ozlabs.ru> | 2014-06-04 22:51:01 +1000 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-06-16 13:24:45 +0200 |
| commit | 4ee4a03b38685be863803e52d9b00ffbc7ce9a22 (patch) | |
| tree | 2297a43ae990bc832cc7c1fec7f03a7a68ffae8d /target-ppc/translate_init.c | |
| parent | 80b3f79b999a334b277137f698c43e7730da4224 (diff) | |
target-ppc: Add POWER8's Event Based Branch (EBB) control SPRs
POWER8 supports Event-Based Branch Facility (EBB). It is controlled via
set of SPRs access to which should generate an "Facility Unavailable"
interrupt if the facilities are not enabled in FSCR for problem state.
This adds EBB SPRs.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/translate_init.c')
| -rw-r--r-- | target-ppc/translate_init.c | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index d31ecc6486..53265532e1 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7717,6 +7717,62 @@ static void gen_spr_power8_tm(CPUPPCState *env) 0x00000000); } +static void spr_read_ebb(void *opaque, int gprn, int sprn) +{ + gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); + spr_read_generic(opaque, gprn, sprn); +} + +static void spr_write_ebb(void *opaque, int sprn, int gprn) +{ + gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); + spr_write_generic(opaque, sprn, gprn); +} + +static void spr_read_ebb_upper32(void *opaque, int gprn, int sprn) +{ + gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); + spr_read_prev_upper32(opaque, gprn, sprn); +} + +static void spr_write_ebb_upper32(void *opaque, int sprn, int gprn) +{ + gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); + spr_write_prev_upper32(opaque, sprn, gprn); +} + +static void gen_spr_power8_ebb(CPUPPCState *env) +{ + spr_register(env, SPR_BESCRS, "BESCRS", + &spr_read_ebb, &spr_write_ebb, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_BESCRSU, "BESCRSU", + &spr_read_ebb_upper32, &spr_write_ebb_upper32, + &spr_read_prev_upper32, &spr_write_prev_upper32, + 0x00000000); + spr_register(env, SPR_BESCRR, "BESCRR", + &spr_read_ebb, &spr_write_ebb, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_BESCRRU, "BESCRRU", + &spr_read_ebb_upper32, &spr_write_ebb_upper32, + &spr_read_prev_upper32, &spr_write_prev_upper32, + 0x00000000); + spr_register_kvm(env, SPR_EBBHR, "EBBHR", + &spr_read_ebb, &spr_write_ebb, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_EBBHR, 0x00000000); + spr_register_kvm(env, SPR_EBBRR, "EBBRR", + &spr_read_ebb, &spr_write_ebb, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_EBBRR, 0x00000000); + spr_register_kvm(env, SPR_BESCR, "BESCR", + &spr_read_ebb, &spr_write_ebb, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_BESCR, 0x00000000); +} + static void gen_spr_power8_fscr(CPUPPCState *env) { #if defined(CONFIG_USER_ONLY) @@ -7775,6 +7831,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version) if (version >= BOOK3S_CPU_POWER8) { gen_spr_power8_tce_address_control(env); gen_spr_power8_ids(env); + gen_spr_power8_ebb(env); gen_spr_power8_fscr(env); gen_spr_power8_pmu_sup(env); gen_spr_power8_pmu_user(env); |