diff options
| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2016-07-27 16:56:41 +1000 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2016-09-07 12:40:10 +1000 |
| commit | 3433b732a4c9abb413eb39a6badb63e83ad2288c (patch) | |
| tree | 82a1c93d253ce3f35acd9de6892e66d2839ffdce /target-ppc/translate.c | |
| parent | b00a3b3648c32cd1d2baaeef6d6a81e8d9341259 (diff) | |
ppc: Make alignment exceptions suck less
The current alignment exception generation tries to load the opcode
to put in DSISR from a context where a cpu_ldl_code() is really not
a good idea. It might fault and longjmp out and that's not something
we want happening here.
Instead, pass the releavant opcode bits via the error_code.
There are a couple of cases of alignment interrupts that won't set
anything, the ones coming from access to direct store segments, but
that doesn't happen in practice, nobody used direct store segments
and they are gone from newer chips.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target-ppc/translate.c')
| -rw-r--r-- | target-ppc/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index bebd1cc490..6bb0ba97ac 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -2417,7 +2417,7 @@ static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) tcg_gen_andi_tl(t0, EA, mask); tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); - t2 = tcg_const_i32(0); + t2 = tcg_const_i32(ctx->opcode & 0x03FF0000); gen_update_nip(ctx, ctx->nip - 4); gen_helper_raise_exception_err(cpu_env, t1, t2); tcg_temp_free_i32(t1); |