diff options
| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2016-06-03 14:11:19 +0200 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2016-06-07 10:17:45 +1000 |
| commit | 932ccbdd48cea5b86f895bdc7d6b409d24aa81cd (patch) | |
| tree | 78404bda8cf2ff2b6f5ab1886751791af30676b4 /target-ppc/translate.c | |
| parent | 1ea1eefcbbcbea91ab295bd5c8c5330d1f458174 (diff) | |
ppc: Better figure out if processor has HV mode
We use an env. flag which is set to the initial value of MSR_HVB in
the msr_mask. We also adjust the POWER8 mask to set SHV.
Also use this to adjust ctx.hv so that it is *set* when the processor
doesn't have an HV mode (970 with Apple mode for example), thus enabling
hypervisor instructions/SPRs.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
[clg: ctx.hv used to be defined only for the hypervisor kernel
(HV=1|PR=0). It is now defined also when PR=1 and conditions are
fixed accordingly.
stripped unwanted tabs.]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target-ppc/translate.c')
| -rw-r--r-- | target-ppc/translate.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 123e42fe6b..c6b74b8540 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -11478,8 +11478,10 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb) ctx.exception = POWERPC_EXCP_NONE; ctx.spr_cb = env->spr_cb; ctx.pr = msr_pr; - ctx.hv = !msr_pr && msr_hv; ctx.mem_idx = env->dmmu_idx; +#if !defined(CONFIG_USER_ONLY) + ctx.hv = msr_hv || !env->has_hv_mode; +#endif ctx.insns_flags = env->insns_flags; ctx.insns_flags2 = env->insns_flags2; ctx.access_type = -1; |