diff options
| author | Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> | 2016-07-26 17:28:33 +0530 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2016-09-07 09:52:14 +1000 |
| commit | b35344e4a0968fd1341ec1c1ed2e6b5c0d851542 (patch) | |
| tree | 57a680bdf56b3a5145c9ad292cc5dea8446103e2 /target-ppc/translate.c | |
| parent | e91d95b27703c6d67370cb3aa78ed5e4f8b03bbb (diff) | |
target-ppc: add cnttzw[.] instruction
Add ISA3.0: Count trailing zeros word instruction.
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target-ppc/translate.c')
| -rw-r--r-- | target-ppc/translate.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 8eea69216e..b24845344e 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -1583,6 +1583,16 @@ static void gen_cntlzw(DisasContext *ctx) if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); } + +/* cnttzw */ +static void gen_cnttzw(DisasContext *ctx) +{ + gen_helper_cnttzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); + if (unlikely(Rc(ctx->opcode) != 0)) { + gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); + } +} + /* eqv & eqv. */ GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); /* extsb & extsb. */ @@ -10057,6 +10067,7 @@ GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), +GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |