diff options
| author | j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-10-26 00:48:00 +0000 |
|---|---|---|
| committer | j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-10-26 00:48:00 +0000 |
| commit | dac454af57c6389c2e3df0b8b51a9b35429d8caa (patch) | |
| tree | 61fd74c2144dc6f2c4e98474aaf2fd34028f452d /target-ppc/translate.c | |
| parent | c7697e1f51025283663c45880587d2da0af31a79 (diff) | |
Bugfix in PowerPC dcbi instruction:
we must do a load before the store, or we'll store random data.
Update cache instructions comments.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3448 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc/translate.c')
| -rw-r--r-- | target-ppc/translate.c | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 54b37ac788..4c5e8c6b98 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -3618,13 +3618,10 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC) } /*** Cache management ***/ -/* For now, all those will be implemented as nop: - * this is valid, regarding the PowerPC specs... - * We just have to flush tb while invalidating instruction cache lines... - */ /* dcbf */ GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE) { + /* XXX: specification says this is treated as a load by the MMU */ gen_addr_reg_index(ctx); op_ldst(lbz); } @@ -3641,7 +3638,7 @@ GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE) } gen_addr_reg_index(ctx); /* XXX: specification says this should be treated as a store by the MMU */ - //op_ldst(lbz); + op_ldst(lbz); op_ldst(stb); #endif } |