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authoraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2008-12-18 22:51:31 +0000
committeraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2008-12-18 22:51:31 +0000
commit564e571add668fefe5e9e5752aa87f721c62efa8 (patch)
treeb8ecc0645f9c7cbf8aa27a328101a744456cd84a /target-ppc/translate.c
parente33e94f92298c96e0928cefab00ea5bae0a1cd19 (diff)
target-ppc: add gen_avr_ptr function.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6098 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc/translate.c')
-rw-r--r--target-ppc/translate.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index a2cd9af2b1..80a08b18ba 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6083,6 +6083,13 @@ GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
/*** Altivec vector extension ***/
/* Altivec registers moves */
+static always_inline TCGv_ptr gen_avr_ptr(int reg)
+{
+ TCGv_ptr r = tcg_temp_new();
+ tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
+ return r;
+}
+
#define GEN_VR_LDX(name, opc2, opc3) \
GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
{ \