diff options
| author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-01-04 22:13:10 +0000 |
|---|---|---|
| committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-01-04 22:13:10 +0000 |
| commit | cbfb6ae9b352c47810ca887011f6a64eaad44ff9 (patch) | |
| tree | 2dc528019fa4ecac652c9eaa62d6d6eb0aa252df /target-ppc/translate.c | |
| parent | bcd2ee23ea2ade96427cada5f2967b769b43f373 (diff) | |
Add {l,st}ve{b,h,w}x instructions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6188 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc/translate.c')
| -rw-r--r-- | target-ppc/translate.c | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 707b493d04..1e82de8a33 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -6144,14 +6144,58 @@ GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \ tcg_temp_free(EA); \ } +#define GEN_VR_LVE(name, opc2, opc3) \ + GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \ + { \ + TCGv EA; \ + TCGv_ptr rs; \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + gen_set_access_type(ctx, ACCESS_INT); \ + EA = tcg_temp_new(); \ + gen_addr_reg_index(ctx, EA); \ + rs = gen_avr_ptr(rS(ctx->opcode)); \ + gen_helper_lve##name (rs, EA); \ + tcg_temp_free(EA); \ + tcg_temp_free_ptr(rs); \ + } + +#define GEN_VR_STVE(name, opc2, opc3) \ + GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \ + { \ + TCGv EA; \ + TCGv_ptr rs; \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + gen_set_access_type(ctx, ACCESS_INT); \ + EA = tcg_temp_new(); \ + gen_addr_reg_index(ctx, EA); \ + rs = gen_avr_ptr(rS(ctx->opcode)); \ + gen_helper_stve##name (rs, EA); \ + tcg_temp_free(EA); \ + tcg_temp_free_ptr(rs); \ + } + GEN_VR_LDX(lvx, 0x07, 0x03); /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */ GEN_VR_LDX(lvxl, 0x07, 0x0B); +GEN_VR_LVE(bx, 0x07, 0x00); +GEN_VR_LVE(hx, 0x07, 0x01); +GEN_VR_LVE(wx, 0x07, 0x02); + GEN_VR_STX(svx, 0x07, 0x07); /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */ GEN_VR_STX(svxl, 0x07, 0x0F); +GEN_VR_STVE(bx, 0x07, 0x04); +GEN_VR_STVE(hx, 0x07, 0x05); +GEN_VR_STVE(wx, 0x07, 0x06); + GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC) { TCGv_ptr rd; |