diff options
| author | Alexander Graf <agraf@suse.de> | 2012-01-31 03:19:23 +0100 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2012-02-02 02:47:47 +0100 |
| commit | d5d11a39a8f761c99276f20974de2f25928830c1 (patch) | |
| tree | f506222b8885da4ee448e477ce42240c6a1833c1 /target-ppc/op_helper.c | |
| parent | 9e0b5cb1ecf5543864fad0628a17be23bb617ed7 (diff) | |
PPC: E500: Implement msgsnd
This patch implements the msgsnd instruction. It is part of the
Embedded.Processor Control specification and allows one CPU to
IPI another CPU without going through an interrupt controller.
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/op_helper.c')
| -rw-r--r-- | target-ppc/op_helper.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c index e2f7614c27..3f4e06789f 100644 --- a/target-ppc/op_helper.c +++ b/target-ppc/op_helper.c @@ -4549,4 +4549,22 @@ void helper_msgclr(target_ulong rb) env->pending_interrupts &= ~(1 << irq); } +void helper_msgsnd(target_ulong rb) +{ + int irq = dbell2irq(rb); + int pir = rb & DBELL_PIRTAG_MASK; + CPUState *cenv; + + if (irq < 0) { + return; + } + + for (cenv = first_cpu; cenv != NULL; cenv = cenv->next_cpu) { + if ((rb & DBELL_BRDCAST) || (cenv->spr[SPR_BOOKE_PIR] == pir)) { + cenv->pending_interrupts |= 1 << irq; + cpu_interrupt(cenv, CPU_INTERRUPT_HARD); + } + } +} + #endif /* !CONFIG_USER_ONLY */ |