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authorj_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162>2007-10-01 05:16:57 +0000
committerj_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162>2007-10-01 05:16:57 +0000
commit7dbe11acd807b7a1566b2fe665333a49f8358de0 (patch)
treeb0c9681451bcb1d5631c564e8a5d6b9bd56bb725 /target-ppc/op.c
parent578bb25230229307c0b6ff62ae03ac0fbda27b18 (diff)
Handle all MMU models in switches, even if it's just to abort because of lack
of supporting code. Implement 74xx software TLB model. Keep 74xx with software TLB disabled, as Linux is not able to handle TLB miss on those processors. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3307 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc/op.c')
-rw-r--r--target-ppc/op.c15
1 files changed, 14 insertions, 1 deletions
diff --git a/target-ppc/op.c b/target-ppc/op.c
index 6ad68eabaa..822c267695 100644
--- a/target-ppc/op.c
+++ b/target-ppc/op.c
@@ -2025,8 +2025,8 @@ void OPPROTO op_slbie_64 (void)
#endif
#endif
-/* PowerPC 602/603/755 software TLB load instructions */
#if !defined(CONFIG_USER_ONLY)
+/* PowerPC 602/603/755 software TLB load instructions */
void OPPROTO op_6xx_tlbld (void)
{
do_load_6xx_tlb(0);
@@ -2038,6 +2038,19 @@ void OPPROTO op_6xx_tlbli (void)
do_load_6xx_tlb(1);
RETURN();
}
+
+/* PowerPC 74xx software TLB load instructions */
+void OPPROTO op_74xx_tlbld (void)
+{
+ do_load_74xx_tlb(0);
+ RETURN();
+}
+
+void OPPROTO op_74xx_tlbli (void)
+{
+ do_load_74xx_tlb(1);
+ RETURN();
+}
#endif
/* 601 specific */