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| author | Anthony Liguori <aliguori@us.ibm.com> | 2013-07-10 10:54:16 -0500 |
|---|---|---|
| committer | Anthony Liguori <aliguori@us.ibm.com> | 2013-07-10 10:54:16 -0500 |
| commit | 51455c59ddc370612f6e070d8eb0e594aaa7ef24 (patch) | |
| tree | a3044bd466cb3a548e6abad273663469bf68647a /target-ppc/mmu_helper.c | |
| parent | 9f9a03b9818194da39c6759d9b0cbee5d7ace4e1 (diff) | |
| parent | 91b1df8cf9e1ecaa8679c9ea8713d1e25c28e6c4 (diff) | |
Merge remote-tracking branch 'afaerber/tags/qom-cpu-for-anthony' into staging
QOM CPUState refactorings
* Fix for OpenRISCCPU subclasses
* Fix for gdbstub CPU selection
* Move linux-user CPU functions into new header
* CPUState part 10 refactoring: first_cpu, next_cpu, cpu_single_env et al.
* Fix some targets to consistently inline TCG code generation
* Centrally log CPU reset
# gpg: Signature made Wed 10 Jul 2013 07:52:39 AM CDT using RSA key ID 3E7E013F
# gpg: Can't check signature: public key not found
# By Andreas Färber (41) and others
# Via Andreas Färber
* afaerber/tags/qom-cpu-for-anthony: (43 commits)
cpu: Move reset logging to CPUState
target-ppc: Change LOG_MMU_STATE() argument to CPUState
target-i386: Change LOG_PCALL_STATE() argument to CPUState
log: Change log_cpu_state[_mask]() argument to CPUState
target-i386: Change do_smm_enter() argument to X86CPU
target-i386: Change do_interrupt_all() argument to X86CPU
target-xtensa: Change gen_intermediate_code_internal() arg to XtensaCPU
target-unicore32: Change gen_intermediate_code_internal() signature
target-sparc: Change gen_intermediate_code_internal() argument to SPARCCPU
target-sh4: Change gen_intermediate_code_internal() argument to SuperHCPU
target-s390x: Change gen_intermediate_code_internal() argument to S390CPU
target-ppc: Change gen_intermediate_code_internal() argument to PowerPCCPU
target-mips: Change gen_intermediate_code_internal() argument to MIPSCPU
target-microblaze: Change gen_intermediate_code_internal() argument types
target-m68k: Change gen_intermediate_code_internal() argument to M68kCPU
target-lm32: Change gen_intermediate_code_internal() argument to LM32CPU
target-i386: Change gen_intermediate_code_internal() argument to X86CPU
target-cris: Change gen_intermediate_code_internal() argument to CRISCPU
target-arm: Change gen_intermediate_code_internal() argument to ARMCPU
target-alpha: Change gen_intermediate_code_internal() argument to AlphaCPU
...
Diffstat (limited to 'target-ppc/mmu_helper.c')
| -rw-r--r-- | target-ppc/mmu_helper.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index 385b67ab23..77102c4b65 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -32,10 +32,10 @@ #ifdef DEBUG_MMU # define LOG_MMU(...) qemu_log(__VA_ARGS__) -# define LOG_MMU_STATE(env) log_cpu_state((env), 0) +# define LOG_MMU_STATE(cpu) log_cpu_state((cpu), 0) #else # define LOG_MMU(...) do { } while (0) -# define LOG_MMU_STATE(...) do { } while (0) +# define LOG_MMU_STATE(cpu) do { } while (0) #endif #ifdef DEBUG_SOFTWARE_TLB @@ -1508,7 +1508,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, mmu_idx, TARGET_PAGE_SIZE); ret = 0; } else if (ret < 0) { - LOG_MMU_STATE(env); + LOG_MMU_STATE(CPU(ppc_env_get_cpu(env))); if (access_type == ACCESS_CODE) { switch (ret) { case -1: @@ -2890,7 +2890,7 @@ void helper_booke206_tlbflush(CPUPPCState *env, uint32_t type) void tlb_fill(CPUPPCState *env, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - CPUState *cpu = ENV_GET_CPU(env); + CPUState *cpu = CPU(ppc_env_get_cpu(env)); PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); int ret; |