diff options
| author | Tom Musta <tommusta@gmail.com> | 2014-12-18 10:34:34 -0600 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2015-01-07 16:16:27 +0100 |
| commit | 0ff93d11bc0890b2569f748266c04f4417ec3233 (patch) | |
| tree | 4c3f6c045177abb53bcfe57a6ec166f3d307892e /target-ppc/mem_helper.c | |
| parent | aac862379ceaa724aba2ba9f4b825479c1401b1a (diff) | |
target-ppc: Introduce tbegin
Provide a degenerate implementation of the tbegin instruction. This
implementation always fails the transaction, recording the failure
per Book II Section 5.3.2 of the Power ISA V2.07.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/mem_helper.c')
| -rw-r--r-- | target-ppc/mem_helper.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c index 50344b81cf..6d37dae7b0 100644 --- a/target-ppc/mem_helper.c +++ b/target-ppc/mem_helper.c @@ -269,3 +269,25 @@ STVE(stvewx, cpu_stl_data, bswap32, u32) #undef HI_IDX #undef LO_IDX + +void helper_tbegin(CPUPPCState *env) +{ + /* As a degenerate implementation, always fail tbegin. The reason + * given is "Nesting overflow". The "persistent" bit is set, + * providing a hint to the error handler to not retry. The TFIAR + * captures the address of the failure, which is this tbegin + * instruction. Instruction execution will continue with the + * next instruction in memory, which is precisely what we want. + */ + + env->spr[SPR_TEXASR] = + (1ULL << TEXASR_FAILURE_PERSISTENT) | + (1ULL << TEXASR_NESTING_OVERFLOW) | + (msr_hv << TEXASR_PRIVILEGE_HV) | + (msr_pr << TEXASR_PRIVILEGE_PR) | + (1ULL << TEXASR_FAILURE_SUMMARY) | + (1ULL << TEXASR_TFIAR_EXACT); + env->spr[SPR_TFIAR] = env->nip | (msr_hv << 1) | msr_pr; + env->spr[SPR_TFHAR] = env->nip + 4; + env->crf[0] = 0xB; /* 0b1010 = transaction failure */ +} |