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authorDavid Gibson <david@gibson.dropbear.id.au>2011-04-01 15:15:08 +1100
committerAlexander Graf <agraf@suse.de>2011-04-01 18:34:54 +0200
commit81762d6dd0d430d87024f2c83e9c4dcc4329fb7d (patch)
treebd081fa7949a578cc91b6aba958cf14a78c108a8 /target-ppc/machine.c
parent17d9b3af5b7f93e43d7fbdcb6f14cad54de9f1ae (diff)
Clean up PowerPC SLB handling code
Currently the SLB information when emulating a PowerPC 970 is storeed in a structure with the unhelpfully named fields 'tmp' and 'tmp64'. While the layout in these fields does match the description of the SLB in the architecture document, it is not convenient either for looking up the SLB, or for emulating the slbmte instruction. This patch, therefore, reorganizes the SLB entry structure to be divided in the the "ESID related" and "VSID related" fields as they are divided in instructions accessing the SLB. In addition to making the code smaller and more readable, this will make it easier to implement for the 1TB segments used in more recent PowerPC chips. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/machine.c')
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