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| author | Alexey Kardashevskiy <aik@ozlabs.ru> | 2014-06-04 22:50:59 +1000 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-06-16 13:24:45 +0200 |
| commit | cdcdda27fc843873875e7e444e0164ba2a5e9942 (patch) | |
| tree | 7b490295f1b369fbe608407ab00e0c5c166d5b88 /target-ppc/helper.h | |
| parent | 70c5340744f044d2195216d0e3c7c0c554dbd7ca (diff) | |
target-ppc: Add POWER8's TM SPRs
This adds TM (Transactional Memory) SPRs.
This adds generic spr_read_prev_upper32()/spr_write_prev_upper32() to
handle upper half SPRs such as TEXASRU which is upper half of TEXASR.
Since this is not the only register like that and their numbers go
consequently, it makes sense to generalize the helpers.
This adds a gen_msr_facility_check() helper which purpose is to generate
the Facility Unavailable exception if the facility is disabled.
It is a copy of gen_fscr_facility_check() but it checks for enabled
facility in MSR rather than FSCR/HFSCR. It still sets the interrupt cause
in FSCR/HFSCR (whichever is passed to the helper).
This adds spr_read_tm/spr_write_tm/spr_read_tm_upper32/spr_write_tm_upper32
which are used for TM SPRs.
This adds TM-relates MSR bits definitions. This enables TM in POWER8 CPU class'
msr_mask.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/helper.h')
| -rw-r--r-- | target-ppc/helper.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-ppc/helper.h b/target-ppc/helper.h index c1417ea75d..509eae52ff 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -578,6 +578,7 @@ DEF_HELPER_3(store_dcr, void, env, tl, tl) DEF_HELPER_2(load_dump_spr, void, env, i32) DEF_HELPER_2(store_dump_spr, void, env, i32) DEF_HELPER_4(fscr_facility_check, void, env, i32, i32, i32) +DEF_HELPER_4(msr_facility_check, void, env, i32, i32, i32) DEF_HELPER_1(load_tbl, tl, env) DEF_HELPER_1(load_tbu, tl, env) DEF_HELPER_1(load_atbl, tl, env) |