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| author | Tom Musta <tommusta@gmail.com> | 2014-11-17 14:58:31 -0600 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2015-01-07 16:16:25 +0100 |
| commit | 2791128e2fa8b96d0b81622404655529b0b4fd4d (patch) | |
| tree | 427d59c65c6b2e2b71303e221f81d13f82a8a780 /target-ppc/fpu_helper.c | |
| parent | cb3778a0455a2e5a48d7ef0ec8dc656313820389 (diff) | |
target-ppc: Load/Store Vector Element Storage Alignment
The Load Vector Element Indexed and Store Vector Element Indexed
instructions compute an effective address in the usual manner.
However, they truncate that address to the natural boundary.
For example, the lvewx instruction will ignore the least significant
two bits of the address and thus load the aligned word of storage.
Fix the generators for these instruction to properly perform this
truncation.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/fpu_helper.c')
0 files changed, 0 insertions, 0 deletions