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| author | j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-03-20 22:11:31 +0000 |
|---|---|---|
| committer | j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-03-20 22:11:31 +0000 |
| commit | 0487d6a8b4e15383d0651eea1e4e03ded44308b2 (patch) | |
| tree | 08fa8a944867ee7df1bb258f93eba421aa5a65d3 /target-ppc/exec.h | |
| parent | 75d62a585629cdc1ae0d530189653cb1d8d9c53c (diff) | |
PowerPC 2.03 SPE extension - first pass.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2519 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc/exec.h')
| -rw-r--r-- | target-ppc/exec.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target-ppc/exec.h b/target-ppc/exec.h index f1dde82d46..a10b62d25b 100644 --- a/target-ppc/exec.h +++ b/target-ppc/exec.h @@ -39,10 +39,10 @@ register unsigned long T1 asm(AREG2); register unsigned long T2 asm(AREG3); #endif /* We may, sometime, need 64 bits registers on 32 bits target */ -#if defined(TARGET_PPC64) || (HOST_LONG_BITS == 64) +#if defined(TARGET_PPC64) || defined(TARGET_PPCSPE) || (HOST_LONG_BITS == 64) #define T0_64 T0 -#define T1_64 T0 -#define T2_64 T0 +#define T1_64 T1 +#define T2_64 T2 #else /* no registers can be used */ #define T0_64 (env->t0) |