diff options
| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2016-05-03 18:03:24 +0200 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2016-05-30 13:20:04 +1000 |
| commit | 9fb044911444fdd09f5f072ad0ca269d7f8b841d (patch) | |
| tree | ce608f84663764e368d651a5713933bb2c2127fd /target-ppc/excp_helper.c | |
| parent | 5fd1111b20a8f1955e3156a80e0576007548e871 (diff) | |
ppc: Use split I/D mmu modes to avoid flushes on interrupts
We rework the way the MMU indices are calculated, providing separate
indices for I and D side based on MSR:IR and MSR:DR respectively,
and thus no longer need to flush the TLB on context changes. This also
adds correct support for HV as a separate address space.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target-ppc/excp_helper.c')
| -rw-r--r-- | target-ppc/excp_helper.c | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c index 288903ee1d..ba3caec699 100644 --- a/target-ppc/excp_helper.c +++ b/target-ppc/excp_helper.c @@ -646,9 +646,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) if (env->spr[SPR_LPCR] & LPCR_AIL) { new_msr |= (1 << MSR_IR) | (1 << MSR_DR); - } else if (msr & ((1 << MSR_IR) | (1 << MSR_DR))) { - /* If we disactivated any translation, flush TLBs */ - tlb_flush(cs, 1); } #ifdef TARGET_PPC64 @@ -721,14 +718,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) /* Reset exception state */ cs->exception_index = POWERPC_EXCP_NONE; env->error_code = 0; - - if ((env->mmu_model == POWERPC_MMU_BOOKE) || - (env->mmu_model == POWERPC_MMU_BOOKE206)) { - /* XXX: The BookE changes address space when switching modes, - we should probably implement that as different MMU indexes, - but for the moment we do it the slow way and flush all. */ - tlb_flush(cs, 1); - } } void ppc_cpu_do_interrupt(CPUState *cs) |