diff options
| author | Alexey Kardashevskiy <aik@ozlabs.ru> | 2014-06-04 22:50:37 +1000 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-06-16 13:24:42 +0200 |
| commit | bbc01ca7f265f2c5be8aee7c9ce1d10aa26063f5 (patch) | |
| tree | 6df0f69a272b8535894ec046b504c1e23a07a0c2 /target-ppc/cpu.h | |
| parent | cb8b8bf840141e2874823b1ee8c0efa98f269708 (diff) | |
target-ppc: Merge 970FX and 970MP into a single 970 class
The differences between classes were:
1. SLB size, was 32 for 970 and 64 for others, should be 64 for all;
2. check_pow() callback, HID0 format is the same so should be the same
0x01C00000 which means "deep nap", "doze" and "nap" bits set;
3. LPCR - 970 does not have it but 970MP had one (by mistake).
This fixes wrong differences and makes one 970 class.
This fixes wrong registration of LPCR which is not present on 970.
This defines HID0 bits and uses them in check_pow_970().
This does not copy MSR_SHV (Hypervisor State, HV) bit from 970FX to
970 class as we do not emulate hypervisor in QEMU anyway.
This does not remove check_pow_970FX now as it is still used by POWER5+
class, this will be addressed later.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/cpu.h')
| -rw-r--r-- | target-ppc/cpu.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index c86793c190..ce3c7903fb 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1727,6 +1727,11 @@ static inline int cpu_mmu_index (CPUPPCState *env) #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ +/* HID0 bits */ +#define HID0_DEEPNAP (1 << 24) +#define HID0_DOZE (1 << 23) +#define HID0_NAP (1 << 22) + /*****************************************************************************/ /* PowerPC Instructions types definitions */ enum { |