diff options
| author | Alexey Kardashevskiy <aik@ozlabs.ru> | 2014-06-04 22:50:43 +1000 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-06-16 13:24:43 +0200 |
| commit | c36c97f8804bbc2cd731f37a159ecdf618600871 (patch) | |
| tree | 39ca3ece62d803f2e8da9861d1b82efdc4d7de36 /target-ppc/cpu.h | |
| parent | 077850b037eea63d9b01db96dd0cb65a46dd0f0f (diff) | |
target-ppc: Add PMC7/8 to 970 class
Compared to PowerISA-compliant CPUs, 970 family has most of them plus
PMC7/8 which are only present on 970 but not on POWER5 and later CPUs.
Since we are changing SPRs for Book3s/970 families, let's add them too.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/cpu.h')
| -rw-r--r-- | target-ppc/cpu.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 531124c541..92e26c854a 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1484,9 +1484,11 @@ static inline int cpu_mmu_index (CPUPPCState *env) #define SPR_PERF9 (0x309) #define SPR_RCPU_L2U_RBA1 (0x309) #define SPR_MPC_MD_CASID (0x309) +#define SPR_970_UPMC7 (0X309) #define SPR_PERFA (0x30A) #define SPR_RCPU_L2U_RBA2 (0x30A) #define SPR_MPC_MD_AP (0x30A) +#define SPR_970_UPMC8 (0X30A) #define SPR_PERFB (0x30B) #define SPR_RCPU_L2U_RBA3 (0x30B) #define SPR_MPC_MD_EPN (0x30B) @@ -1519,7 +1521,9 @@ static inline int cpu_mmu_index (CPUPPCState *env) #define SPR_UPERF8 (0x318) #define SPR_POWER_PMC6 (0X318) #define SPR_UPERF9 (0x319) +#define SPR_970_PMC7 (0X319) #define SPR_UPERFA (0x31A) +#define SPR_970_PMC8 (0X31A) #define SPR_UPERFB (0x31B) #define SPR_POWER_MMCR0 (0X31B) #define SPR_UPERFC (0x31C) |