diff options
| author | Alexey Kardashevskiy <aik@ozlabs.ru> | 2014-06-04 22:50:55 +1000 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-06-16 13:24:44 +0200 |
| commit | d1a721ab816d1b954c0988aafdec4e109b953a9f (patch) | |
| tree | dcb64980cc93a87f9b3319f1321f79b7302b9b5f /target-ppc/cpu.h | |
| parent | a242881405811ec6e6134452311f1cd1896c8ada (diff) | |
target-ppc: Add POWER8's TIR SPR
This adds TIR (Thread Identification Register) SPR first defined for server
CPUs in PowerISA 2.07.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/cpu.h')
| -rw-r--r-- | target-ppc/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 6a53d70af5..9f9ffb174d 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1370,6 +1370,7 @@ static inline int cpu_mmu_index (CPUPPCState *env) #define SPR_BOOKE_GIVOR8 (0x1BB) #define SPR_BOOKE_GIVOR13 (0x1BC) #define SPR_BOOKE_GIVOR14 (0x1BD) +#define SPR_TIR (0x1BE) #define SPR_BOOKE_SPEFSCR (0x200) #define SPR_Exxx_BBEAR (0x201) #define SPR_Exxx_BBTAR (0x202) |