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| author | Pierre Mallard <mallard.pierre@gmail.com> | 2014-09-12 21:31:32 +0200 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-11-04 23:26:11 +0100 |
| commit | 4171853cf4dfb88da93bf77a4c9d319d6ba2bdc6 (patch) | |
| tree | 4e7026c384efb5ef6151123c1c91ddfd4ccbf084 /target-ppc/cpu.h | |
| parent | 9ac58dc59aaf9db20ec17df9b372915bee9b0f02 (diff) | |
target-ppc : Allow fc[tf]id[*] mnemonics for non TARGET_PPC64
This patch remove limitation for fc[tf]id[*] on 32 bits targets and
add a new insn flag for signed integer 64 conversion PPC2_FP_CVT_S64
Signed-off-by: Pierre Mallard <mallard.pierre@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/cpu.h')
| -rw-r--r-- | target-ppc/cpu.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 872456171f..f367344475 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -2007,13 +2007,16 @@ enum { PPC2_ALTIVEC_207 = 0x0000000000004000ULL, /* PowerISA 2.07 Book3s specification */ PPC2_ISA207S = 0x0000000000008000ULL, + /* Double precision floating point conversion for signed integer 64 */ + PPC2_FP_CVT_S64 = 0x0000000000010000ULL, #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \ PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \ PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \ - PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP) + PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \ + PPC2_FP_CVT_S64) }; /*****************************************************************************/ |