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| author | Alexander Graf <agraf@suse.de> | 2014-01-19 17:47:43 +0100 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-06-16 13:24:34 +0200 |
| commit | d2ea2bf740c515de41f45e4d6f36683db3458881 (patch) | |
| tree | ad7e50ba8cda7d373f831e95ec56842c41ac46c7 /target-ppc/cpu.h | |
| parent | deb05c4c4c2b7bfeccddb8494164cc858a8652ec (diff) | |
PPC: Add L1CFG1 SPR emulation
In addition to the L1 data cache configuration register L1CFG0 there is
also another one for the L1 instruction cache called L1CFG1.
Emulate that one with the same values as the data one.
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/cpu.h')
| -rw-r--r-- | target-ppc/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 178fc55689..f36c90b47b 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1375,6 +1375,7 @@ static inline int cpu_mmu_index (CPUPPCState *env) #define SPR_Exxx_BBEAR (0x201) #define SPR_Exxx_BBTAR (0x202) #define SPR_Exxx_L1CFG0 (0x203) +#define SPR_Exxx_L1CFG1 (0x204) #define SPR_Exxx_NPIDR (0x205) #define SPR_ATBL (0x20E) #define SPR_ATBU (0x20F) |