diff options
author | j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-14 18:45:52 +0000 |
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committer | j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-14 18:45:52 +0000 |
commit | 57c26279c7bdef3cb181ea0afbd062a87d4ed6a0 (patch) | |
tree | 7577cd3c7e3e1c9bc3018bd6e4f5fd931f2e3ee9 /target-ppc/cpu.h | |
parent | d2fd1af76777687697674e7a49eeceac83907f3e (diff) |
Fix PowerPC targets compilation on 32 bits hosts:
now that the SPE extension is available for all targets,
we always need to have some 64 bits temporary registers.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3647 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc/cpu.h')
-rw-r--r-- | target-ppc/cpu.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 7589ba2159..bb50c1df66 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -520,11 +520,11 @@ struct CPUPPCState { /* First are the most commonly used resources * during translated code execution */ -#if TARGET_GPR_BITS > HOST_LONG_BITS +#if (HOST_LONG_BITS == 32) /* temporary fixed-point registers - * used to emulate 64 bits target on 32 bits hosts + * used to emulate 64 bits registers on 32 bits hosts */ - ppc_gpr_t t0, t1, t2; + uint64_t t0, t1, t2; #endif ppc_avr_t avr0, avr1, avr2; |