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| author | Andreas Färber <afaerber@suse.de> | 2013-06-27 19:09:09 +0200 |
|---|---|---|
| committer | Andreas Färber <afaerber@suse.de> | 2013-07-23 02:41:33 +0200 |
| commit | f3659eee05793aede68b1791465fb2b0767bc1f2 (patch) | |
| tree | 626440326fd54bc46ac8bc77750798787d388f79 /target-openrisc | |
| parent | f17ec444c3d39f76bcd8b71c2c05d5754bfe333e (diff) | |
cpu: Introduce CPUClass::memory_rw_debug() for target_memory_rw_debug()
Make inline target_memory_rw_debug() always available and change its
argument to CPUState. Let it check if CPUClass::memory_rw_debug provides
a specialized callback and fall back to cpu_memory_rw_debug() otherwise.
The only overriding implementation is for 32-bit sparc.
This prepares for changing GDBState::g_cpu to CPUState.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-openrisc')
0 files changed, 0 insertions, 0 deletions