aboutsummaryrefslogtreecommitdiff
path: root/target-openrisc
diff options
context:
space:
mode:
authorAurelien Jarno <aurelien@aurel32.net>2012-10-09 21:53:11 +0200
committerAurelien Jarno <aurelien@aurel32.net>2012-11-24 13:19:53 +0100
commit7aab08aa786e3a8838beac758ee61c5000144937 (patch)
tree7b05548fe1c860313b666d43a66c78f4cbd4ccb5 /target-openrisc
parentd17bd1d8cc27f8c1a24c65f555a77a661c332b7f (diff)
tcg/arm: fix cross-endian qemu_st16
The bswap16 TCG opcode assumes that the high bytes of the temp equal to 0 before calling it. The ARM backend implementation takes this assumption to slightly optimize the generated code. The same implementation is called for implementing the cross-endian qemu_st16 opcode, where this assumption is not true anymore. One way to fix that would be to zero the high bytes before calling it. Given the store instruction just ignore them, it is possible to provide a slightly more optimized version. With ARMv6+ the rev16 instruction does the work correctly. For lower ARM versions the patch provides a version which behaves correctly with non-zero high bytes, but fill them with junk. Cc: Andrzej Zaborowski <balrogg@gmail.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-openrisc')
0 files changed, 0 insertions, 0 deletions