diff options
| author | Jia Liu <proljc@gmail.com> | 2012-07-20 15:50:49 +0800 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2012-07-27 21:13:03 +0000 |
| commit | 4dd044c6ba8b957899f0f308ab43ad61a27d26d4 (patch) | |
| tree | 68983918642a4b791fee6659513f8097c9ccdb17 /target-openrisc/translate.c | |
| parent | ce6e1e9ec9b54811a942d6aece92fab3f5ace88d (diff) | |
target-or32: Add system instructions
Add OpenRISC system instructions.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-openrisc/translate.c')
| -rw-r--r-- | target-openrisc/translate.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index a17455dec2..325ba09cb5 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -997,10 +997,36 @@ static void dec_misc(DisasContext *dc, uint32_t insn) case 0x2d: /* l.mfspr */ LOG_DIS("l.mfspr r%d, r%d, %d\n", rd, ra, I16); + { +#if defined(CONFIG_USER_ONLY) + return; +#else + TCGv_i32 ti = tcg_const_i32(I16); + if (dc->mem_idx == MMU_USER_IDX) { + gen_illegal_exception(dc); + return; + } + gen_helper_mfspr(cpu_R[rd], cpu_env, cpu_R[rd], cpu_R[ra], ti); + tcg_temp_free_i32(ti); +#endif + } break; case 0x30: /* l.mtspr */ LOG_DIS("l.mtspr %d, r%d, r%d, %d\n", I5, ra, rb, I11); + { +#if defined(CONFIG_USER_ONLY) + return; +#else + TCGv_i32 im = tcg_const_i32(tmp); + if (dc->mem_idx == MMU_USER_IDX) { + gen_illegal_exception(dc); + return; + } + gen_helper_mtspr(cpu_env, cpu_R[ra], cpu_R[rb], im); + tcg_temp_free_i32(im); +#endif + } break; /* not used yet, open it when we need or64. */ |