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| author | Tom Musta <tommusta@gmail.com> | 2014-12-18 10:34:35 -0600 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2015-01-07 16:16:27 +0100 |
| commit | 56a846157edaba3389eb141e104774451d82ce51 (patch) | |
| tree | 31a96bb3ec72a229b86a7e6380cb0512507a02b2 /target-openrisc/interrupt.c | |
| parent | 0ff93d11bc0890b2569f748266c04f4417ec3233 (diff) | |
target-ppc: Introduce TM Noops
Add degenerate implementations of the non-privileged Transactional
Memory instructions tend., tabort*. and tsr. This implementation
simply checks the MSR[TM] bit and then sets CR0 to 0b0000. This
is a reasonable degenerate implementation since transactions are
never allowed to begin and hence MSR[TS] is always 0b00.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-openrisc/interrupt.c')
0 files changed, 0 insertions, 0 deletions