diff options
| author | Jia Liu <proljc@gmail.com> | 2012-07-20 15:50:41 +0800 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2012-07-27 21:12:57 +0000 |
| commit | b6a71ef7e01bcac7aeb47d8de4082704fbc6479c (patch) | |
| tree | 3ae466a65ec1083a2575b5d3cbb92139e9b98742 /target-openrisc/cpu.h | |
| parent | 726fe04572093504e7bf4ea56e0b2de559063787 (diff) | |
target-or32: Add interrupt support
Add OpenRISC interrupt support.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-openrisc/cpu.h')
| -rw-r--r-- | target-openrisc/cpu.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index 9423e7786a..51013f3fc1 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -83,6 +83,9 @@ enum { /* Internal flags, delay slot flag */ #define D_FLAG 1 +/* Interrupt */ +#define NR_IRQS 32 + /* Registers */ enum { R0 = 0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, @@ -309,6 +312,7 @@ typedef struct CPUOpenRISCState { uint32_t picmr; /* Interrupt mask register */ uint32_t picsr; /* Interrupt contrl register*/ #endif + void *irq[32]; /* Interrupt irq input */ } CPUOpenRISCState; /** @@ -392,9 +396,11 @@ static inline int cpu_mmu_index(CPUOpenRISCState *env) return (env->sr & SR_SM) == 0 ? MMU_USER_IDX : MMU_SUPERVISOR_IDX; } +#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0 static inline bool cpu_has_work(CPUOpenRISCState *env) { - return true; + return env->interrupt_request & (CPU_INTERRUPT_HARD | + CPU_INTERRUPT_TIMER); } #include "exec-all.h" |