aboutsummaryrefslogtreecommitdiff
path: root/target-openrisc/cpu.h
diff options
context:
space:
mode:
authorBastian Koppelmann <kbastian@mail.uni-paderborn.de>2016-02-19 14:43:46 +0100
committerBastian Koppelmann <kbastian@mail.uni-paderborn.de>2016-02-25 12:54:50 +0100
commit828066c78a02a98bc395d125002b2d7a888285bb (patch)
tree202b2a9afd99d652b0349d71feabf815f7921b0c /target-openrisc/cpu.h
parentf678f671ba654d4610f0e43d175c8c1b2fad10df (diff)
target-tricore: add opd trap generation
If an instruction uses a 64 bit register which consists of an even-odd pair of 32 bit registers and if the register specifier in the instruction is odd an opd trap is raised. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <1455889426-1923-5-git-send-email-kbastian@mail.uni-paderborn.de>
Diffstat (limited to 'target-openrisc/cpu.h')
0 files changed, 0 insertions, 0 deletions