diff options
| author | Jia Liu <proljc@gmail.com> | 2012-07-20 15:50:47 +0800 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2012-07-27 21:13:02 +0000 |
| commit | 99f575edccdd81e0f17863814c5867867ba67846 (patch) | |
| tree | 9bb1eabd911e99f20671b1882058d2b0ffde15cc /target-openrisc/cpu.h | |
| parent | dd29c7fb0189cb2415bee3f411afcfcf9290e466 (diff) | |
target-or32: Add timer support
Add OpenRISC timer support.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-openrisc/cpu.h')
| -rw-r--r-- | target-openrisc/cpu.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index 419c31ab44..df07eaf666 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -220,6 +220,22 @@ enum { OPENRISC_FEATURE_OV64S = (1 << 9), }; +/* Tick Timer Mode Register */ +enum { + TTMR_TP = (0xfffffff), + TTMR_IP = (1 << 28), + TTMR_IE = (1 << 29), + TTMR_M = (3 << 30), +}; + +/* Timer Mode */ +enum { + TIMER_NONE = (0 << 30), + TIMER_INTR = (1 << 30), + TIMER_SHOT = (2 << 30), + TIMER_CONT = (3 << 30), +}; + /* TLB size */ enum { DTLB_WAYS = 1, @@ -358,6 +374,12 @@ int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env, /* hw/openrisc_pic.c */ void cpu_openrisc_pic_init(OpenRISCCPU *cpu); +/* hw/openrisc_timer.c */ +void cpu_openrisc_clock_init(OpenRISCCPU *cpu); +void cpu_openrisc_count_update(OpenRISCCPU *cpu); +void cpu_openrisc_count_start(OpenRISCCPU *cpu); +void cpu_openrisc_count_stop(OpenRISCCPU *cpu); + void cpu_openrisc_mmu_init(OpenRISCCPU *cpu); int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu, target_phys_addr_t *physical, |