target-mips: fix indentation

Remove all tabs from target-mips/*

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6306 c046a42c-6fe2-441c-8c8c-71466251a162

4 files changed, 98 insertions, 98 deletions

diff --git a/target-mips/helper.c b/target-mips/helper.c
index c4fd9574e6..344d431354 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -134,18 +134,18 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
 #if defined(TARGET_MIPS64)
     } else if (address < 0x4000000000000000ULL) {
         /* xuseg */
-	if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
+        if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
-	} else {
-	    ret = TLBRET_BADADDR;
+        } else {
+            ret = TLBRET_BADADDR;
         }
     } else if (address < 0x8000000000000000ULL) {
         /* xsseg */
-	if ((supervisor_mode || kernel_mode) &&
-	    SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
+        if ((supervisor_mode || kernel_mode) &&
+            SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
-	} else {
-	    ret = TLBRET_BADADDR;
+        } else {
+            ret = TLBRET_BADADDR;
         }
     } else if (address < 0xC000000000000000ULL) {
         /* xkphys */
@@ -153,17 +153,17 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
             (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
             *physical = address & env->PAMask;
             *prot = PAGE_READ | PAGE_WRITE;
-	} else {
-	    ret = TLBRET_BADADDR;
-	}
+        } else {
+            ret = TLBRET_BADADDR;
+        }
     } else if (address < 0xFFFFFFFF80000000ULL) {
         /* xkseg */
-	if (kernel_mode && KX &&
-	    address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
+        if (kernel_mode && KX &&
+            address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
-	} else {
-	    ret = TLBRET_BADADDR;
-	}
+        } else {
+            ret = TLBRET_BADADDR;
+        }
 #endif
     } else if (address < (int32_t)0xA0000000UL) {
         /* kseg0 */
@@ -200,7 +200,7 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
 #if 0
     if (logfile) {
         fprintf(logfile, TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
-		address, rw, access_type, *physical, *prot, ret);
+                address, rw, access_type, *physical, *prot, ret);
     }
 #endif
 
@@ -297,7 +297,7 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
         /* Raise exception */
         env->CP0_BadVAddr = address;
         env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
-	                   ((address >> 9) &   0x007ffff0);
+                           ((address >> 9) &   0x007ffff0);
         env->CP0_EntryHi =
             (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
 #if defined(TARGET_MIPS64)
@@ -593,8 +593,8 @@ void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
 
     if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
         /* For tlbwr, we can shadow the discarded entry into
-	   a new (fake) TLB entry, as long as the guest can not
-	   tell that it's there.  */
+           a new (fake) TLB entry, as long as the guest can not
+           tell that it's there.  */
         env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
         env->tlb->tlb_in_use++;
         return;
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 3c994992c7..f09d8fecbb 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -1518,7 +1518,7 @@ target_ulong do_yield(target_ulong t0)
             }
         }
     } else if (t0 == 0) {
-	if (0 /* TODO: TC underflow */) {
+        if (0 /* TODO: TC underflow */) {
             env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
             do_raise_exception(EXCP_THREAD);
         } else {
@@ -1622,17 +1622,17 @@ void r4k_do_tlbp (void)
     if (i == env->tlb->nb_tlb) {
         /* No match.  Discard any shadow entries, if any of them match.  */
         for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
-	    tlb = &env->tlb->mmu.r4k.tlb[i];
-	    /* 1k pages are not supported. */
-	    mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
-	    tag = env->CP0_EntryHi & ~mask;
-	    VPN = tlb->VPN & ~mask;
-	    /* Check ASID, virtual page number & size */
-	    if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
+            tlb = &env->tlb->mmu.r4k.tlb[i];
+            /* 1k pages are not supported. */
+            mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
+            tag = env->CP0_EntryHi & ~mask;
+            VPN = tlb->VPN & ~mask;
+            /* Check ASID, virtual page number & size */
+            if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
                 r4k_mips_tlb_flush_extra (env, i);
-	        break;
-	    }
-	}
+                break;
+            }
+        }
 
         env->CP0_Index |= 0x80000000;
     }
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 4a1861f7ee..19893a5ef4 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1092,7 +1092,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
         break;
     case OPC_LWL:
         save_cpu_state(ctx, 1);
-	gen_load_gpr(t1, rt);
+        gen_load_gpr(t1, rt);
         gen_helper_3i(lwl, t1, t0, t1, ctx->mem_idx);
         gen_store_gpr(t1, rt);
         opn = "lwl";
@@ -1105,7 +1105,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
         break;
     case OPC_LWR:
         save_cpu_state(ctx, 1);
-	gen_load_gpr(t1, rt);
+        gen_load_gpr(t1, rt);
         gen_helper_3i(lwr, t1, t0, t1, ctx->mem_idx);
         gen_store_gpr(t1, rt);
         opn = "lwr";
@@ -2076,59 +2076,59 @@ static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc,
     case OPC_VR54XX_MULS:
         gen_helper_muls(t0, t0, t1);
         opn = "muls";
-	break;
+        break;
     case OPC_VR54XX_MULSU:
         gen_helper_mulsu(t0, t0, t1);
         opn = "mulsu";
-	break;
+        break;
     case OPC_VR54XX_MACC:
         gen_helper_macc(t0, t0, t1);
         opn = "macc";
-	break;
+        break;
     case OPC_VR54XX_MACCU:
         gen_helper_maccu(t0, t0, t1);
         opn = "maccu";
-	break;
+        break;
     case OPC_VR54XX_MSAC:
         gen_helper_msac(t0, t0, t1);
         opn = "msac";
-	break;
+        break;
     case OPC_VR54XX_MSACU:
         gen_helper_msacu(t0, t0, t1);
         opn = "msacu";
-	break;
+        break;
     case OPC_VR54XX_MULHI:
         gen_helper_mulhi(t0, t0, t1);
         opn = "mulhi";
-	break;
+        break;
     case OPC_VR54XX_MULHIU:
         gen_helper_mulhiu(t0, t0, t1);
         opn = "mulhiu";
-	break;
+        break;
     case OPC_VR54XX_MULSHI:
         gen_helper_mulshi(t0, t0, t1);
         opn = "mulshi";
-	break;
+        break;
     case OPC_VR54XX_MULSHIU:
         gen_helper_mulshiu(t0, t0, t1);
         opn = "mulshiu";
-	break;
+        break;
     case OPC_VR54XX_MACCHI:
         gen_helper_macchi(t0, t0, t1);
         opn = "macchi";
-	break;
+        break;
     case OPC_VR54XX_MACCHIU:
         gen_helper_macchiu(t0, t0, t1);
         opn = "macchiu";
-	break;
+        break;
     case OPC_VR54XX_MSACHI:
         gen_helper_msachi(t0, t0, t1);
         opn = "msachi";
-	break;
+        break;
     case OPC_VR54XX_MSACHIU:
         gen_helper_msachiu(t0, t0, t1);
         opn = "msachiu";
-	break;
+        break;
     default:
         MIPS_INVAL("mul vr54xx");
         generate_exception(ctx, EXCP_RI);
@@ -2323,7 +2323,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
             fprintf(logfile,
                     "Branch in delay slot at PC 0x" TARGET_FMT_lx "\n",
                     ctx->pc);
-	}
+        }
 #endif
         generate_exception(ctx, EXCP_RI);
         goto out;
@@ -5763,7 +5763,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
             gen_load_fpr32(fp0, fs);
             tcg_gen_ext_i32_tl(t0, fp0);
             tcg_temp_free_i32(fp0);
-	}
+        }
         gen_store_gpr(t0, rt);
         opn = "mfc1";
         break;
@@ -5775,7 +5775,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
             tcg_gen_trunc_tl_i32(fp0, t0);
             gen_store_fpr32(fp0, fs);
             tcg_temp_free_i32(fp0);
-	}
+        }
         opn = "mtc1";
         break;
     case OPC_CFC1:
@@ -5795,7 +5795,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
             gen_load_fpr64(ctx, fp0, fs);
             tcg_gen_trunc_i64_tl(t0, fp0);
             tcg_temp_free_i64(fp0);
-	}
+        }
         gen_store_gpr(t0, rt);
         opn = "dmfc1";
         break;
@@ -5807,7 +5807,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
             tcg_gen_extu_tl_i64(fp0, t0);
             gen_store_fpr64(ctx, fp0, fs);
             tcg_temp_free_i64(fp0);
-	}
+        }
         opn = "dmtc1";
         break;
     case OPC_MFHC1:
@@ -5817,7 +5817,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
             gen_load_fpr32h(fp0, fs);
             tcg_gen_ext_i32_tl(t0, fp0);
             tcg_temp_free_i32(fp0);
-	}
+        }
         gen_store_gpr(t0, rt);
         opn = "mfhc1";
         break;
@@ -5829,7 +5829,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
             tcg_gen_trunc_tl_i32(fp0, t0);
             gen_store_fpr32h(fp0, fs);
             tcg_temp_free_i32(fp0);
-	}
+        }
         opn = "mthc1";
         break;
     default:
@@ -8339,7 +8339,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
         save_cpu_state(&ctx, ctx.bstate == BS_NONE);
         gen_helper_0i(raise_exception, EXCP_DEBUG);
     } else {
-	switch (ctx.bstate) {
+        switch (ctx.bstate) {
         case BS_STOP:
             gen_helper_interrupt_restart();
             gen_goto_tb(&ctx, 0, ctx.pc);
@@ -8355,7 +8355,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
         case BS_BRANCH:
         default:
             break;
-	}
+        }
     }
 done_generating:
     gen_icount_end(tb, num_insns);
@@ -8499,7 +8499,7 @@ static void mips_tcg_init(void)
 
     /* Initialize various static tables. */
     if (inited)
-	return;
+        return;
 
     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
     for (i = 0; i < 32; i++)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index d0243aa1d9..1400414a16 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -102,8 +102,8 @@ static const mips_def_t mips_defs[] =
         .CP0_PRid = 0x00018000,
         .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
         .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
-		    (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
-		    (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
+                       (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+                       (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
         .CP0_Config2 = MIPS_CONFIG2,
         .CP0_Config3 = MIPS_CONFIG3,
         .SYNCI_Step = 32,
@@ -121,8 +121,8 @@ static const mips_def_t mips_defs[] =
            no virtual icache, uncached coherency. */
         .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
         .CP0_Config1 = MIPS_CONFIG1 |
-		    (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
-		    (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
+                       (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+                       (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
         .CP0_Config2 = MIPS_CONFIG2,
         .CP0_Config3 = MIPS_CONFIG3,
         .SYNCI_Step = 32,
@@ -138,8 +138,8 @@ static const mips_def_t mips_defs[] =
         .CP0_PRid = 0x00018400,
         .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
         .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
-		    (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
-		    (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
+                       (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+                       (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
         .CP0_Config2 = MIPS_CONFIG2,
         .CP0_Config3 = MIPS_CONFIG3,
         .SYNCI_Step = 32,
@@ -155,8 +155,8 @@ static const mips_def_t mips_defs[] =
         .CP0_PRid = 0x00018500,
         .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
         .CP0_Config1 = MIPS_CONFIG1 |
-		    (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
-		    (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
+                       (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+                       (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
         .CP0_Config2 = MIPS_CONFIG2,
         .CP0_Config3 = MIPS_CONFIG3,
         .SYNCI_Step = 32,
@@ -173,8 +173,8 @@ static const mips_def_t mips_defs[] =
         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
                     (MMU_TYPE_R4000 << CP0C0_MT),
         .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
-		    (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
-		    (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
+                       (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+                       (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
         .CP0_Config2 = MIPS_CONFIG2,
         .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
         .SYNCI_Step = 32,
@@ -189,10 +189,10 @@ static const mips_def_t mips_defs[] =
         .name = "4KEm",
         .CP0_PRid = 0x00019100,
         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
-                    (MMU_TYPE_FMT << CP0C0_MT),
+                       (MMU_TYPE_FMT << CP0C0_MT),
         .CP0_Config1 = MIPS_CONFIG1 |
-		    (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
-		    (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
+                       (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+                       (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
         .CP0_Config2 = MIPS_CONFIG2,
         .CP0_Config3 = MIPS_CONFIG3,
         .SYNCI_Step = 32,
@@ -207,10 +207,10 @@ static const mips_def_t mips_defs[] =
         .name = "24Kc",
         .CP0_PRid = 0x00019300,
         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
-                    (MMU_TYPE_R4000 << CP0C0_MT),
+                       (MMU_TYPE_R4000 << CP0C0_MT),
         .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
-		    (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
-		    (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
+                       (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+                       (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
         .CP0_Config2 = MIPS_CONFIG2,
         .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
         .SYNCI_Step = 32,
@@ -228,8 +228,8 @@ static const mips_def_t mips_defs[] =
         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
                     (MMU_TYPE_R4000 << CP0C0_MT),
         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
-		    (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
-		    (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
+                       (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+                       (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
         .CP0_Config2 = MIPS_CONFIG2,
         .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
         .SYNCI_Step = 32,
@@ -247,10 +247,10 @@ static const mips_def_t mips_defs[] =
         .name = "34Kf",
         .CP0_PRid = 0x00019500,
         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
-                    (MMU_TYPE_R4000 << CP0C0_MT),
+                       (MMU_TYPE_R4000 << CP0C0_MT),
         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
-		    (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
-		    (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
+                       (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+                       (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
         .CP0_Config2 = MIPS_CONFIG2,
         .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_MT),
         .SYNCI_Step = 32,
@@ -293,12 +293,12 @@ static const mips_def_t mips_defs[] =
         .CP0_PRid = 0x00000400,
         /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
         .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
-	/* Note: Config1 is only used internally, the R4000 has only Config0. */
+        /* Note: Config1 is only used internally, the R4000 has only Config0. */
         .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
         .SYNCI_Step = 16,
         .CCRes = 2,
         .CP0_Status_rw_bitmask = 0x3678FFFF,
-	/* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
+        /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
         .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
         .SEGBITS = 40,
         .PABITS = 36,
@@ -325,11 +325,11 @@ static const mips_def_t mips_defs[] =
         .name = "5Kc",
         .CP0_PRid = 0x00018100,
         .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
-                    (MMU_TYPE_R4000 << CP0C0_MT),
+                       (MMU_TYPE_R4000 << CP0C0_MT),
         .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
-		    (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
-		    (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
-		    (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+                       (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
+                       (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
+                       (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
         .CP0_Config2 = MIPS_CONFIG2,
         .CP0_Config3 = MIPS_CONFIG3,
         .SYNCI_Step = 32,
@@ -344,17 +344,17 @@ static const mips_def_t mips_defs[] =
         .name = "5Kf",
         .CP0_PRid = 0x00018100,
         .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
-                    (MMU_TYPE_R4000 << CP0C0_MT),
+                       (MMU_TYPE_R4000 << CP0C0_MT),
         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
-		    (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
-		    (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
-		    (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+                       (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
+                       (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
+                       (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
         .CP0_Config2 = MIPS_CONFIG2,
         .CP0_Config3 = MIPS_CONFIG3,
         .SYNCI_Step = 32,
         .CCRes = 2,
         .CP0_Status_rw_bitmask = 0x36F8FFFF,
-	/* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
+        /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
         .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
                     (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
         .SEGBITS = 42,
@@ -364,21 +364,21 @@ static const mips_def_t mips_defs[] =
     },
     {
         .name = "20Kc",
-	/* We emulate a later version of the 20Kc, earlier ones had a broken
+        /* We emulate a later version of the 20Kc, earlier ones had a broken
            WAIT instruction. */
         .CP0_PRid = 0x000182a0,
         .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
                     (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
-		    (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
-		    (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
-		    (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+                       (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
+                       (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
+                       (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
         .CP0_Config2 = MIPS_CONFIG2,
         .CP0_Config3 = MIPS_CONFIG3,
         .SYNCI_Step = 32,
         .CCRes = 1,
         .CP0_Status_rw_bitmask = 0x36FBFFFF,
-	/* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
+        /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
         .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
                     (1 << FCR0_D) | (1 << FCR0_S) |
                     (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
@@ -388,16 +388,16 @@ static const mips_def_t mips_defs[] =
         .mmu_type = MMU_TYPE_R4000,
     },
     {
-	/* A generic CPU providing MIPS64 Release 2 features.
+        /* A generic CPU providing MIPS64 Release 2 features.
            FIXME: Eventually this should be replaced by a real CPU model. */
         .name = "MIPS64R2-generic",
         .CP0_PRid = 0x00010000,
         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
-                    (MMU_TYPE_R4000 << CP0C0_MT),
+                       (MMU_TYPE_R4000 << CP0C0_MT),
         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
-		    (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
-		    (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
-		    (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+                       (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
+                       (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
+                       (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
         .CP0_Config2 = MIPS_CONFIG2,
         .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
         .SYNCI_Step = 32,