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| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-06-22 23:50:19 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-06-22 23:50:19 +0000 |
| commit | 17044c06b846e84191534a8a8f8bdc56a2b2e619 (patch) | |
| tree | 1ae242a9284072fb42984b1e697aa66893ad4cbd /target-mips | |
| parent | 7bfd934a13636a7bb611dd282959efde28d92faf (diff) | |
Allow emulation of 32bit targets in the MIPS64 capable qemu version.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3007 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/translate_init.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index e576ef865a..5d25e57466 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -77,7 +77,6 @@ struct mips_def_t { /* MIPS CPU definitions */ static mips_def_t mips_defs[] = { -#ifndef TARGET_MIPS64 { .name = "4Kc", .CP0_PRid = 0x00018000, @@ -135,7 +134,7 @@ static mips_def_t mips_defs[] = .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), }, -#else +#ifdef TARGET_MIPS64 { .name = "R4000", .CP0_PRid = 0x00000400, |