diff options
| author | Stefan Weil <sw@weilnetz.de> | 2012-04-07 09:23:37 +0200 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2012-04-07 13:58:25 +0000 |
| commit | 6576b74b0ba068f252cc23c5a541c59621270483 (patch) | |
| tree | 47510209823790c319e808436efbe74cb9c55a7b /target-mips | |
| parent | 071c93945825dcf8b8ec0d81f09e631d7c96142d (diff) | |
Replace Qemu by QEMU in internal documentation
The official spelling is QEMU.
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/TODO | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target-mips/TODO b/target-mips/TODO index 9101881a97..2a3546f624 100644 --- a/target-mips/TODO +++ b/target-mips/TODO @@ -16,7 +16,7 @@ General Existing documentation is x86-centric. - Reverse endianness bit not implemented - The TLB emulation is very inefficient: - Qemu's softmmu implements a x86-style MMU, with separate entries + QEMU's softmmu implements a x86-style MMU, with separate entries for read/write/execute, a TLB index which is just a modulo of the virtual address, and a set of TLBs for each user/kernel/supervisor MMU mode. @@ -25,7 +25,7 @@ General up to 256 ASID tags as additional matching criterion (which roughly equates to 256 MMU modes). It also has a global flag which causes entries to match regardless of ASID. - To cope with these differences, Qemu currently flushes the TLB at + To cope with these differences, QEMU currently flushes the TLB at each ASID change. Using the MMU modes to implement ASIDs hinges on implementing the global bit efficiently. - save/restore of the CPU state is not implemented (see machine.c). |